In the semiconductor industry it is often necessary to physically analyze semiconductor integrated circuits (ICs) for the purposes of product reliability assurance, design validation and identification of device structural patterns. ICs are analyzed to extract design and/or layout information therefrom. This process is known as reverse-engineering. Reverse-engineering is also part of the test and development process in the manufacture of ICs on a large scale. In general, a vast amount of time and manual labor is required to reverse-engineer an IC.
An IC is a monocrystalline silicon die upon which a large number of transistors and other electronic components have been fabricated and interconnected to form a useful circuit. During manufacture, each die is part of a larger silicon wafer substrate which facilitates handling and simultaneous processing of a plurality of ICs.
The IC fabrication process includes: doping the silicon substrate to change its conductive properties and building up a sequence of layers onto the silicon substrate using different techniques. Doping layers are created using ion implantation. Diffusion layers are created by depositing dopants on top of a substrate and heating the wafer. With each deposition layer, different materials are deposited and selectively removed by selective etching in accordance with a predetermined pattern. Components manufactured on the silicon wafer span multiple layers. Oxide layers are used for insulation. Deposited metal layers are used to interconnect individual terminals of the components so formed. It is the identification of these components and the interconnections provided by the metal layers that provides base information from which the design and/or layout of an IC can be extracted and verified.
In reverse-engineering a sample IC, the die is deconstructed. The IC sample die is subjected to a progressive layer-removal sequence utilizing an exacting series treatment, such as etchants, each of which is specifically chosen to remove a single layer at a time. Other deconstructing treatments include dry etching, polishing, etc. Using such treatments, interconnecting metal layers, polycrystalline silicon layers, oxide layers, etc. are removed step-by-step. At each step in the deconstruction of a chip, the surface of the partly deconstructed IC is inspected.
Inspection techniques include the use of: optical microscopes, scanning electron microscopes, and other surface inspection equipment. In general, the scanning electron microscope is accurate but is expensive to own and operate. Optical microscopes can be used in brightfield, contrast interference and darkfield modes of illumination. In the brightfield or contrast interference modes, the physical extents of the components on the die are distorted by fringe effects. These fringe effects can be interpreted by an experienced human analyst but require vast amounts of computation for analysis by a computer.
A METHOD OF EXAMINING MICROCIRCUIT PATTERNS is described in the U.S. Pat. No. 4,623,255 which issued Nov. 18, 1986 to Suszko. The method involves photographing an IC die in between deprocessing steps. Film transparencies are printed and used by an engineer analyst to extract design and layout information from the photographed IC. While the teachings of Suszko have merit, design and layout extraction are impeded by the handling and cross-correlation of the bulky transparencies.
Human enabled extraction of design and layout information from image-mosaics is lengthy. Other prior art methods concentrate on eliminating human input from the information extraction process by devising image analysis algorithms.
An AUTOMATED SYSTEM FOR EXTRACTING DESIGN AND LAYOUT INFORMATION FROM AN INTEGRATED CIRCUIT is described by Yu et al. in U.S. Pat. No. 5,086,477 which issued Feb. 4, 1992. A digital camera and a controlled stage are used to capture images in overlapping tile fashion after each deconstruction step. The captured digital images are stored in a computer memory and reassembled into image-mosaics based on the overlap at the borders of each tile image. Yu et al. describe pattern matching performed on an image-mosaic captured after a deconstruction step, and points out the difficulties involved in extracting layout information from the tile images. The automated system to Yu et al. appears to be suitable for extracting design information from complex ICs that are difficult to reverse engineer. To accomplish this, “cell” libraries are built. The cell libraries contain images of specific arrangements of components that are known to perform a specific function. The cell libraries are used for automated pattern matching in order to facilitate reverse engineering of Application Specific Integrated Circuits (ASICs), for example. However, Yu et al. fail to describe how multiple image-mosaics, each representing a different step in the deconstruction of an IC, are manipulated in order to extract design and layout information concurrently therefrom. Concurrent analysis of image-mosaics is desirable because individual components fabricated on the silicon wafer may span multiple layers.
Another prior art publication in PROCEEDINGS OF THE 5TH INTERNATIONAL SYMPOSIUM ON IC TECHNOLOGY, SYSTEM AND APPLICATIONS, SINGAPORE by Tan Ooi Kiang et al. entitled “INTEGRATED CIRCUIT CHIP LAYER ANALYSIS” (presented 15–17 Sep. 1993) describes a system for automatic layout extraction from IC's achieving a quoted 85% accuracy. The remainder of the extracted layout being left for completion by a human engineer analyst.
While such automated systems are ingenious, it is debatable whether such automated design and layout extraction methods are superior to or more economical than human driven processes.
There therefore is a need to provide improved methods and apparatus enabling an engineer analyst to extract design and layout information from image-mosaics in a time efficient, enhanced manner.